1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to a pipelined processor core with reconfigurable architecture in which a parallel execution slice issue queue is linked for executing instructions of differing width.
2. Description of Related Art
In present-day processor cores, pipelines are used to execute multiple hardware threads corresponding to multiple instruction streams so that more efficient use of processor resources can be provided through resource sharing, and by allowing execution to proceed even while one or more hardware threads are waiting on an event.
Typical execution pipelines are set up to execute instructions of fixed width, or to execute portions of vector instructions in parallel, since the control logic to manage the execution of instructions is typically fixed. Such architectures are constrained to their fixed instruction execution architecture and when a parallel processor is executing non-vector instructions, processor resources are typically not being used.
It would therefore be desirable to provide a processor core for processing program instructions that provide improved used of the processor core resources.